URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_22/] - Rev 83

Rev	Log message	Author	Age	Path
52	Trst signal is not inverted here any more. Inverted on higher layer !!!.	mohor	7920d 14h	/dbg_interface/tags/rel_22/
51	WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated.	mohor	7948d 02h	/dbg_interface/tags/rel_22/
50	Revision 1.5 of the document ready. WISHBONE Scan Chain changed.	mohor	7948d 02h	/dbg_interface/tags/rel_22/
47	mon_cntl_o signals that controls monitor mux added.	mohor	8103d 13h	/dbg_interface/tags/rel_22/
46	Asynchronous reset used instead of synchronous.	mohor	8111d 20h	/dbg_interface/tags/rel_22/
45	tdo_padoen_o changed to tdo_padoe_o. Signal is active high.	mohor	8118d 15h	/dbg_interface/tags/rel_22/
44	Signal names changed to lower case.	mohor	8118d 15h	/dbg_interface/tags/rel_22/
43	Intentional error removed.	mohor	8123d 15h	/dbg_interface/tags/rel_22/
42	A block for checking possible simulation/synthesis missmatch added.	mohor	8123d 17h	/dbg_interface/tags/rel_22/
41	Function changed to logic because of some synthesis warnings.	mohor	8131d 14h	/dbg_interface/tags/rel_22/