URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_6/] [rtl/] - Rev 53

Rev	Log message	Author	Age	Path
27	Warnings from synthesys tools fixed.	mohor	8272d 05h	/dbg_interface/tags/rel_6/rtl/
26	Warnings from synthesys tools fixed.	mohor	8272d 05h	/dbg_interface/tags/rel_6/rtl/
25	trst signal is synchronized to wb_clk_i.	mohor	8273d 02h	/dbg_interface/tags/rel_6/rtl/
23	Trace disabled by default.	mohor	8280d 06h	/dbg_interface/tags/rel_6/rtl/
22	Register length fixed.	mohor	8280d 06h	/dbg_interface/tags/rel_6/rtl/
21	CRC is returned when chain selection data is transmitted.	mohor	8281d 02h	/dbg_interface/tags/rel_6/rtl/
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8282d 04h	/dbg_interface/tags/rel_6/rtl/
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8294d 05h	/dbg_interface/tags/rel_6/rtl/
18	Reset signals are not combined any more.	mohor	8296d 14h	/dbg_interface/tags/rel_6/rtl/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8320d 04h	/dbg_interface/tags/rel_6/rtl/