URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rel_8/] - Rev 39

Rev	Log message	Author	Age	Path
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8259d 09h	/dbg_interface/tags/rel_8/
18	Reset signals are not combined any more.	mohor	8261d 18h	/dbg_interface/tags/rel_8/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8285d 08h	/dbg_interface/tags/rel_8/
16	bs_chain_o port added.	mohor	8287d 07h	/dbg_interface/tags/rel_8/
15	bs_chain_o added.	mohor	8287d 09h	/dbg_interface/tags/rel_8/
14	Document updated.	mohor	8288d 06h	/dbg_interface/tags/rel_8/
13	Signal names changed to lowercase.	mohor	8288d 09h	/dbg_interface/tags/rel_8/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8289d 09h	/dbg_interface/tags/rel_8/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8310d 05h	/dbg_interface/tags/rel_8/
10	First official release 1.0.	mohor	8314d 09h	/dbg_interface/tags/rel_8/