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[/] [dbg_interface/] [tags/] [rel_8/] - Rev 40

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Rev Log message Author Age Path
20 Crc generation is different for read or write commands. Small synthesys fixes. mohor 8255d 22h /dbg_interface/tags/rel_8/
19 Wishbone data latched on wb_clk_i instead of risc_clk. mohor 8267d 23h /dbg_interface/tags/rel_8/
18 Reset signals are not combined any more. mohor 8270d 08h /dbg_interface/tags/rel_8/
17 dbg_timescale.v changed to timescale.v This is done for the simulation of
few different cores in a single project.
mohor 8293d 21h /dbg_interface/tags/rel_8/
16 bs_chain_o port added. mohor 8295d 21h /dbg_interface/tags/rel_8/
15 bs_chain_o added. mohor 8295d 22h /dbg_interface/tags/rel_8/
14 Document updated. mohor 8296d 20h /dbg_interface/tags/rel_8/
13 Signal names changed to lowercase. mohor 8296d 23h /dbg_interface/tags/rel_8/
12 Wishbone interface added, few fixes for better performance,
hooks for boundary scan testing added.
mohor 8297d 23h /dbg_interface/tags/rel_8/
11 Changes connected to the OpenRISC access (SPR read, SPR write). mohor 8318d 19h /dbg_interface/tags/rel_8/

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