OpenCores
URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [rev_23/] [rtl/] - Rev 99

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
63 Three more chains added for cpu debug access. simons 7619d 09h /dbg_interface/tags/rev_23/rtl/
61 Lapsus fixed. simons 7647d 09h /dbg_interface/tags/rev_23/rtl/
59 Reset value for riscsel register set to 1. simons 7647d 09h /dbg_interface/tags/rev_23/rtl/
57 Multiple cpu support added. simons 7647d 11h /dbg_interface/tags/rev_23/rtl/
53 Trst active high. Inverted on higher layer. mohor 7914d 08h /dbg_interface/tags/rev_23/rtl/
52 Trst signal is not inverted here any more. Inverted on higher layer !!!. mohor 7914d 09h /dbg_interface/tags/rev_23/rtl/
51 WISHBONE Scan Chain is changed to reflect state of the WISHBONE access (WBInProgress bit added). Internal counter is used (counts 256 wb_clk cycles) and when counter exceeds that value, wb_cyc_o is negated. mohor 7941d 20h /dbg_interface/tags/rev_23/rtl/
47 mon_cntl_o signals that controls monitor mux added. mohor 8097d 08h /dbg_interface/tags/rev_23/rtl/
46 Asynchronous reset used instead of synchronous. mohor 8105d 14h /dbg_interface/tags/rev_23/rtl/
45 tdo_padoen_o changed to tdo_padoe_o. Signal is active high. mohor 8112d 10h /dbg_interface/tags/rev_23/rtl/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.