URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] - Rev 42

Rev	Log message	Author	Age	Path
22	Register length fixed.	mohor	8265d 23h	/dbg_interface/tags/sdram_test_working/
21	CRC is returned when chain selection data is transmitted.	mohor	8266d 19h	/dbg_interface/tags/sdram_test_working/
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8267d 22h	/dbg_interface/tags/sdram_test_working/
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8279d 22h	/dbg_interface/tags/sdram_test_working/
18	Reset signals are not combined any more.	mohor	8282d 07h	/dbg_interface/tags/sdram_test_working/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8305d 21h	/dbg_interface/tags/sdram_test_working/
16	bs_chain_o port added.	mohor	8307d 21h	/dbg_interface/tags/sdram_test_working/
15	bs_chain_o added.	mohor	8307d 22h	/dbg_interface/tags/sdram_test_working/
14	Document updated.	mohor	8308d 20h	/dbg_interface/tags/sdram_test_working/
13	Signal names changed to lowercase.	mohor	8308d 22h	/dbg_interface/tags/sdram_test_working/