URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] - Rev 49

Rev	Log message	Author	Age	Path
28	TDO and TDO Enable signal are separated into two signals.	mohor	8243d 22h	/dbg_interface/tags/sdram_test_working/
27	Warnings from synthesys tools fixed.	mohor	8257d 23h	/dbg_interface/tags/sdram_test_working/
26	Warnings from synthesys tools fixed.	mohor	8257d 23h	/dbg_interface/tags/sdram_test_working/
25	trst signal is synchronized to wb_clk_i.	mohor	8258d 19h	/dbg_interface/tags/sdram_test_working/
24	CRC changed so more thorough testing is done.	mohor	8259d 21h	/dbg_interface/tags/sdram_test_working/
23	Trace disabled by default.	mohor	8265d 23h	/dbg_interface/tags/sdram_test_working/
22	Register length fixed.	mohor	8265d 23h	/dbg_interface/tags/sdram_test_working/
21	CRC is returned when chain selection data is transmitted.	mohor	8266d 19h	/dbg_interface/tags/sdram_test_working/
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8267d 22h	/dbg_interface/tags/sdram_test_working/
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8279d 23h	/dbg_interface/tags/sdram_test_working/