URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] - Rev 43

Rev	Log message	Author	Age	Path
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8261d 17h	/dbg_interface/tags/sdram_test_working/rtl/
18	Reset signals are not combined any more.	mohor	8264d 02h	/dbg_interface/tags/sdram_test_working/rtl/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8287d 16h	/dbg_interface/tags/sdram_test_working/rtl/
15	bs_chain_o added.	mohor	8289d 17h	/dbg_interface/tags/sdram_test_working/rtl/
13	Signal names changed to lowercase.	mohor	8290d 17h	/dbg_interface/tags/sdram_test_working/rtl/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8291d 18h	/dbg_interface/tags/sdram_test_working/rtl/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8312d 13h	/dbg_interface/tags/sdram_test_working/rtl/
9	Working version. Few bugs fixed, comments added.	mohor	8316d 17h	/dbg_interface/tags/sdram_test_working/rtl/
8	Asynchronous set/reset not used in trace any more.	mohor	8317d 16h	/dbg_interface/tags/sdram_test_working/rtl/
5	Trace fixed. Some registers changed, trace simplified.	mohor	8318d 13h	/dbg_interface/tags/sdram_test_working/rtl/