URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] - Rev 44

Rev	Log message	Author	Age	Path
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8259d 10h	/dbg_interface/tags/sdram_test_working/rtl/
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8271d 11h	/dbg_interface/tags/sdram_test_working/rtl/
18	Reset signals are not combined any more.	mohor	8273d 19h	/dbg_interface/tags/sdram_test_working/rtl/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8297d 09h	/dbg_interface/tags/sdram_test_working/rtl/
15	bs_chain_o added.	mohor	8299d 10h	/dbg_interface/tags/sdram_test_working/rtl/
13	Signal names changed to lowercase.	mohor	8300d 11h	/dbg_interface/tags/sdram_test_working/rtl/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8301d 11h	/dbg_interface/tags/sdram_test_working/rtl/
11	Changes connected to the OpenRISC access (SPR read, SPR write).	mohor	8322d 07h	/dbg_interface/tags/sdram_test_working/rtl/
9	Working version. Few bugs fixed, comments added.	mohor	8326d 10h	/dbg_interface/tags/sdram_test_working/rtl/
8	Asynchronous set/reset not used in trace any more.	mohor	8327d 09h	/dbg_interface/tags/sdram_test_working/rtl/