URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] - Rev 47

Rev	Log message	Author	Age	Path
23	Trace disabled by default.	mohor	8247d 17h	/dbg_interface/tags/sdram_test_working/rtl/
22	Register length fixed.	mohor	8247d 17h	/dbg_interface/tags/sdram_test_working/rtl/
21	CRC is returned when chain selection data is transmitted.	mohor	8248d 13h	/dbg_interface/tags/sdram_test_working/rtl/
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8249d 16h	/dbg_interface/tags/sdram_test_working/rtl/
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8261d 17h	/dbg_interface/tags/sdram_test_working/rtl/
18	Reset signals are not combined any more.	mohor	8264d 02h	/dbg_interface/tags/sdram_test_working/rtl/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8287d 15h	/dbg_interface/tags/sdram_test_working/rtl/
15	bs_chain_o added.	mohor	8289d 16h	/dbg_interface/tags/sdram_test_working/rtl/
13	Signal names changed to lowercase.	mohor	8290d 17h	/dbg_interface/tags/sdram_test_working/rtl/
12	Wishbone interface added, few fixes for better performance, hooks for boundary scan testing added.	mohor	8291d 17h	/dbg_interface/tags/sdram_test_working/rtl/