URL https://opencores.org/ocsvn/dbg_interface/dbg_interface/trunk

Subversion Repositories dbg_interface

[/] [dbg_interface/] [tags/] [sdram_test_working/] [rtl/] [verilog/] - Rev 158

Rev	Log message	Author	Age	Path
26	Warnings from synthesys tools fixed.	mohor	8273d 10h	/dbg_interface/tags/sdram_test_working/rtl/verilog/
25	trst signal is synchronized to wb_clk_i.	mohor	8274d 07h	/dbg_interface/tags/sdram_test_working/rtl/verilog/
23	Trace disabled by default.	mohor	8281d 11h	/dbg_interface/tags/sdram_test_working/rtl/verilog/
22	Register length fixed.	mohor	8281d 11h	/dbg_interface/tags/sdram_test_working/rtl/verilog/
21	CRC is returned when chain selection data is transmitted.	mohor	8282d 07h	/dbg_interface/tags/sdram_test_working/rtl/verilog/
20	Crc generation is different for read or write commands. Small synthesys fixes.	mohor	8283d 09h	/dbg_interface/tags/sdram_test_working/rtl/verilog/
19	Wishbone data latched on wb_clk_i instead of risc_clk.	mohor	8295d 10h	/dbg_interface/tags/sdram_test_working/rtl/verilog/
18	Reset signals are not combined any more.	mohor	8297d 19h	/dbg_interface/tags/sdram_test_working/rtl/verilog/
17	dbg_timescale.v changed to timescale.v This is done for the simulation of few different cores in a single project.	mohor	8321d 09h	/dbg_interface/tags/sdram_test_working/rtl/verilog/
15	bs_chain_o added.	mohor	8323d 10h	/dbg_interface/tags/sdram_test_working/rtl/verilog/