URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [branches/] [unneback/] [rtl/] [verilog/] - Rev 63

Rev	Log message	Author	Age	Path
39	Tx part finished. TxStatus needs to be fixed. Pause request needs to be added.	mohor	8171d 01h	/ethmac/branches/unneback/rtl/verilog/
38	Initial version. Equals to eth_wishbonedma.v at this moment.	mohor	8180d 03h	/ethmac/branches/unneback/rtl/verilog/
37	Link in the header changed.	mohor	8180d 03h	/ethmac/branches/unneback/rtl/verilog/
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8228d 22h	/ethmac/branches/unneback/rtl/verilog/
33	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8229d 03h	/ethmac/branches/unneback/rtl/verilog/
32	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8229d 03h	/ethmac/branches/unneback/rtl/verilog/
29	Generic memory model is used. Defines are changed for the same reason.	mohor	8250d 23h	/ethmac/branches/unneback/rtl/verilog/
24	Log file added.	mohor	8276d 02h	/ethmac/branches/unneback/rtl/verilog/
23	Number of addresses (wb_adr_i) minimized.	mohor	8276d 02h	/ethmac/branches/unneback/rtl/verilog/
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8276d 05h	/ethmac/branches/unneback/rtl/verilog/