URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_10/] [rtl/] [verilog/] - Rev 118

Rev	Log message	Author	Age	Path
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8144d 12h	/ethmac/tags/rel_10/rtl/verilog/
91	Comments in Slovene language removed.	mohor	8144d 12h	/ethmac/tags/rel_10/rtl/verilog/
90	casex changed with case, fifo reset changed.	mohor	8144d 12h	/ethmac/tags/rel_10/rtl/verilog/
88	rx_fifo was not always cleared ok. Fixed.	mohor	8154d 09h	/ethmac/tags/rel_10/rtl/verilog/
87	Status was not latched correctly sometimes. Fixed.	mohor	8154d 11h	/ethmac/tags/rel_10/rtl/verilog/
86	Big Endian problem when sending frames fixed.	mohor	8155d 18h	/ethmac/tags/rel_10/rtl/verilog/
85	Log info was missing.	mohor	8161d 04h	/ethmac/tags/rel_10/rtl/verilog/
84	LinkFail signal was not latching appropriate bit.	mohor	8161d 04h	/ethmac/tags/rel_10/rtl/verilog/
83	MAC address recognition was not correct (bytes swaped).	mohor	8161d 04h	/ethmac/tags/rel_10/rtl/verilog/
82	Byte ordering changed (Big Endian used). casex changed with case because Xilinx Foundation had problems. Tested in HW. It WORKS.	mohor	8161d 06h	/ethmac/tags/rel_10/rtl/verilog/