URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_12/] [rtl/] [verilog/] - Rev 96

Rev	Log message	Author	Age	Path
74	Reset values are passed to registers through parameters	mohor	8146d 08h	/ethmac/tags/rel_12/rtl/verilog/
73	Number of interrupts changed	mohor	8146d 08h	/ethmac/tags/rel_12/rtl/verilog/
72	Retry is not activated when a Tx Underrun occured	mohor	8150d 11h	/ethmac/tags/rel_12/rtl/verilog/
70	Small fixes.	mohor	8154d 13h	/ethmac/tags/rel_12/rtl/verilog/
69	Define missmatch fixed.	mohor	8155d 10h	/ethmac/tags/rel_12/rtl/verilog/
68	Registered trimmed. Unused registers removed.	mohor	8156d 10h	/ethmac/tags/rel_12/rtl/verilog/
67	EXTERNAL_DMA used instead of WISHBONE_DMA.	mohor	8156d 11h	/ethmac/tags/rel_12/rtl/verilog/
65	Testbench fixed, code simplified, unused signals removed.	mohor	8156d 17h	/ethmac/tags/rel_12/rtl/verilog/
64	Status was not written correctly when frames were discarted because of address mismatch.	mohor	8157d 07h	/ethmac/tags/rel_12/rtl/verilog/
63	RxAbort is connected differently.	mohor	8157d 10h	/ethmac/tags/rel_12/rtl/verilog/