URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_13/] [rtl/] [verilog/] - Rev 160

Rev	Log message	Author	Age	Path
127	WriteRxDataToMemory signal changed so end of frame (when last word is written to fifo) is changed.	mohor	8039d 12h	/ethmac/tags/rel_13/rtl/verilog/
126	InvalidSymbol generation changed.	mohor	8039d 12h	/ethmac/tags/rel_13/rtl/verilog/
125	RxAbort changed. Packets received with MRxErr (from PHY) are also aborted.	mohor	8039d 12h	/ethmac/tags/rel_13/rtl/verilog/
122	ethernet spram added. So far a generic ram and xilinx RAMB4 are used.	mohor	8041d 14h	/ethmac/tags/rel_13/rtl/verilog/
120	Unused files removed.	mohor	8041d 15h	/ethmac/tags/rel_13/rtl/verilog/
119	Ram , used for BDs changed from generic_spram to eth_spram_256x32.	mohor	8041d 15h	/ethmac/tags/rel_13/rtl/verilog/
118	ShiftEnded synchronization changed.	mohor	8045d 06h	/ethmac/tags/rel_13/rtl/verilog/
115	RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset.	mohor	8046d 14h	/ethmac/tags/rel_13/rtl/verilog/
114	EXTERNAL_DMA removed. External DMA not supported.	mohor	8047d 11h	/ethmac/tags/rel_13/rtl/verilog/
113	RxPointer bug fixed.	mohor	8054d 03h	/ethmac/tags/rel_13/rtl/verilog/