URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_16/] [rtl/] [verilog/] - Rev 282

Rev	Log message	Author	Age	Path
244	r_Rst signal does not reset any module any more and is removed from the design.	mohor	7926d 17h	/ethmac/tags/rel_16/rtl/verilog/
242	Late collision is reported only when not in the full duplex. Sample is taken (for status) as soon as MRxDV is not valid (regardless of the received byte cnt).	tadejm	7927d 13h	/ethmac/tags/rel_16/rtl/verilog/
241	StartIdle state changed (not important the size of the packet). StartData1 activates only while ByteCnt is smaller than the MaxFrame.	tadejm	7927d 13h	/ethmac/tags/rel_16/rtl/verilog/
240	All modules are reset with wb_rst instead of the r_Rst. Exception is MII module.	tadejm	7927d 13h	/ethmac/tags/rel_16/rtl/verilog/
239	RxError is not generated when small frame reception is enabled and small frames are received.	tadejm	7927d 13h	/ethmac/tags/rel_16/rtl/verilog/
238	Defines fixed to use generic RAM by default.	mohor	7939d 17h	/ethmac/tags/rel_16/rtl/verilog/
236	State machine goes from idle to the defer state when CarrierSense is 1. FCS (CRC appending) fixed to check the CrcEn bit also when padding is necessery.	mohor	7941d 22h	/ethmac/tags/rel_16/rtl/verilog/
232	fpga define added.	mohor	7947d 16h	/ethmac/tags/rel_16/rtl/verilog/
229	case changed to casex.	mohor	7953d 14h	/ethmac/tags/rel_16/rtl/verilog/
227	Changed BIST scan signals.	tadejm	7953d 18h	/ethmac/tags/rel_16/rtl/verilog/