OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] - Rev 150

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
125 RxAbort changed. Packets received with MRxErr (from PHY) are also
aborted.
mohor 7983d 20h /ethmac/tags/rel_17/rtl/verilog/
122 ethernet spram added. So far a generic ram and xilinx RAMB4 are used. mohor 7985d 22h /ethmac/tags/rel_17/rtl/verilog/
120 Unused files removed. mohor 7985d 23h /ethmac/tags/rel_17/rtl/verilog/
119 Ram , used for BDs changed from generic_spram to eth_spram_256x32. mohor 7985d 23h /ethmac/tags/rel_17/rtl/verilog/
118 ShiftEnded synchronization changed. mohor 7989d 14h /ethmac/tags/rel_17/rtl/verilog/
115 RxBDAddress takes `ETH_TX_BD_NUM_DEF value after reset. mohor 7990d 22h /ethmac/tags/rel_17/rtl/verilog/
114 EXTERNAL_DMA removed. External DMA not supported. mohor 7991d 20h /ethmac/tags/rel_17/rtl/verilog/
113 RxPointer bug fixed. mohor 7998d 12h /ethmac/tags/rel_17/rtl/verilog/
112 Previous bug wasn't succesfully removed. Now fixed. mohor 7999d 01h /ethmac/tags/rel_17/rtl/verilog/
111 Master state machine had a bug when switching from master write to
master read.
mohor 7999d 15h /ethmac/tags/rel_17/rtl/verilog/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.