URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_17/] [rtl/] [verilog/] - Rev 67

Rev	Log message	Author	Age	Path
42	Rx status is written back to the BD.	mohor	8171d 19h	/ethmac/tags/rel_17/rtl/verilog/
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8173d 21h	/ethmac/tags/rel_17/rtl/verilog/
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8174d 18h	/ethmac/tags/rel_17/rtl/verilog/
39	Tx part finished. TxStatus needs to be fixed. Pause request needs to be added.	mohor	8178d 22h	/ethmac/tags/rel_17/rtl/verilog/
38	Initial version. Equals to eth_wishbonedma.v at this moment.	mohor	8188d 00h	/ethmac/tags/rel_17/rtl/verilog/
37	Link in the header changed.	mohor	8188d 01h	/ethmac/tags/rel_17/rtl/verilog/
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8236d 20h	/ethmac/tags/rel_17/rtl/verilog/
33	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8237d 00h	/ethmac/tags/rel_17/rtl/verilog/
32	ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead.	mohor	8237d 01h	/ethmac/tags/rel_17/rtl/verilog/
29	Generic memory model is used. Defines are changed for the same reason.	mohor	8258d 21h	/ethmac/tags/rel_17/rtl/verilog/