URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_18/] [bench/] [verilog/] - Rev 192

Rev	Log message	Author	Age	Path
108	Testbench supports unaligned accesses.	mohor	8078d 16h	/ethmac/tags/rel_18/bench/verilog/
107	TX_BUF_BASE changed.	mohor	8078d 16h	/ethmac/tags/rel_18/bench/verilog/
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8123d 13h	/ethmac/tags/rel_18/bench/verilog/
80	Small fixes for external/internal DMA missmatches.	mohor	8144d 09h	/ethmac/tags/rel_18/bench/verilog/
67	EXTERNAL_DMA used instead of WISHBONE_DMA.	mohor	8154d 13h	/ethmac/tags/rel_18/bench/verilog/
66	Testbench fixed, code simplified, unused signals removed.	mohor	8154d 19h	/ethmac/tags/rel_18/bench/verilog/
51	Added separate tests for Multicast, Unicast, Broadcast	billditt	8156d 06h	/ethmac/tags/rel_18/bench/verilog/
49	HASH0 and HASH1 register read/write added.	mohor	8158d 06h	/ethmac/tags/rel_18/bench/verilog/
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8164d 12h	/ethmac/tags/rel_18/bench/verilog/
36	TX_BD_NUM register added instead of the RB_BD_ADDR.	mohor	8224d 13h	/ethmac/tags/rel_18/bench/verilog/