URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_19/] [bench/] [verilog/] - Rev 192

Rev	Log message	Author	Age	Path
108	Testbench supports unaligned accesses.	mohor	8068d 03h	/ethmac/tags/rel_19/bench/verilog/
107	TX_BUF_BASE changed.	mohor	8068d 04h	/ethmac/tags/rel_19/bench/verilog/
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8113d 01h	/ethmac/tags/rel_19/bench/verilog/
80	Small fixes for external/internal DMA missmatches.	mohor	8133d 21h	/ethmac/tags/rel_19/bench/verilog/
67	EXTERNAL_DMA used instead of WISHBONE_DMA.	mohor	8144d 01h	/ethmac/tags/rel_19/bench/verilog/
66	Testbench fixed, code simplified, unused signals removed.	mohor	8144d 07h	/ethmac/tags/rel_19/bench/verilog/
51	Added separate tests for Multicast, Unicast, Broadcast	billditt	8145d 18h	/ethmac/tags/rel_19/bench/verilog/
49	HASH0 and HASH1 register read/write added.	mohor	8147d 17h	/ethmac/tags/rel_19/bench/verilog/
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8154d 00h	/ethmac/tags/rel_19/bench/verilog/
36	TX_BD_NUM register added instead of the RB_BD_ADDR.	mohor	8214d 01h	/ethmac/tags/rel_19/bench/verilog/