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[/] [ethmac/] [tags/] [rel_19/] [rtl/] [verilog/] - Rev 63

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39 Tx part finished. TxStatus needs to be fixed. Pause request needs to be
added.
mohor 8169d 20h /ethmac/tags/rel_19/rtl/verilog/
38 Initial version. Equals to eth_wishbonedma.v at this moment. mohor 8178d 22h /ethmac/tags/rel_19/rtl/verilog/
37 Link in the header changed. mohor 8178d 22h /ethmac/tags/rel_19/rtl/verilog/
34 RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors
instead of the number of RX descriptors).
mohor 8227d 17h /ethmac/tags/rel_19/rtl/verilog/
33 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8227d 22h /ethmac/tags/rel_19/rtl/verilog/
32 ETH_RX_BD_ADR register deleted. ETH_RX_BD_NUM is used instead. mohor 8227d 22h /ethmac/tags/rel_19/rtl/verilog/
29 Generic memory model is used. Defines are changed for the same reason. mohor 8249d 18h /ethmac/tags/rel_19/rtl/verilog/
24 Log file added. mohor 8274d 21h /ethmac/tags/rel_19/rtl/verilog/
23 Number of addresses (wb_adr_i) minimized. mohor 8274d 21h /ethmac/tags/rel_19/rtl/verilog/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 8275d 00h /ethmac/tags/rel_19/rtl/verilog/

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