URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_20/] [bench/] [verilog/] - Rev 189

Rev	Log message	Author	Age	Path
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8111d 22h	/ethmac/tags/rel_20/bench/verilog/
80	Small fixes for external/internal DMA missmatches.	mohor	8132d 18h	/ethmac/tags/rel_20/bench/verilog/
67	EXTERNAL_DMA used instead of WISHBONE_DMA.	mohor	8142d 22h	/ethmac/tags/rel_20/bench/verilog/
66	Testbench fixed, code simplified, unused signals removed.	mohor	8143d 04h	/ethmac/tags/rel_20/bench/verilog/
51	Added separate tests for Multicast, Unicast, Broadcast	billditt	8144d 15h	/ethmac/tags/rel_20/bench/verilog/
49	HASH0 and HASH1 register read/write added.	mohor	8146d 15h	/ethmac/tags/rel_20/bench/verilog/
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8152d 21h	/ethmac/tags/rel_20/bench/verilog/
36	TX_BD_NUM register added instead of the RB_BD_ADDR.	mohor	8212d 23h	/ethmac/tags/rel_20/bench/verilog/
23	Number of addresses (wb_adr_i) minimized.	mohor	8263d 00h	/ethmac/tags/rel_20/bench/verilog/
22	eth_timescale.v changed to timescale.v This is done because of the simulation of the few cores in a one joined project.	mohor	8263d 03h	/ethmac/tags/rel_20/bench/verilog/