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92 Some defines that are used in testbench only were moved to tb_eth_defines.v
file.
mohor 8134d 16h /ethmac/tags/rel_24/bench/verilog/
80 Small fixes for external/internal DMA missmatches. mohor 8155d 12h /ethmac/tags/rel_24/bench/verilog/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8165d 16h /ethmac/tags/rel_24/bench/verilog/
66 Testbench fixed, code simplified, unused signals removed. mohor 8165d 22h /ethmac/tags/rel_24/bench/verilog/
51 Added separate tests for Multicast, Unicast, Broadcast billditt 8167d 09h /ethmac/tags/rel_24/bench/verilog/
49 HASH0 and HASH1 register read/write added. mohor 8169d 09h /ethmac/tags/rel_24/bench/verilog/
41 non-DMA host interface added. Select the right configutation in eth_defines. mohor 8175d 15h /ethmac/tags/rel_24/bench/verilog/
36 TX_BD_NUM register added instead of the RB_BD_ADDR. mohor 8235d 16h /ethmac/tags/rel_24/bench/verilog/
23 Number of addresses (wb_adr_i) minimized. mohor 8285d 18h /ethmac/tags/rel_24/bench/verilog/
22 eth_timescale.v changed to timescale.v This is done because of the
simulation of the few cores in a one joined project.
mohor 8285d 20h /ethmac/tags/rel_24/bench/verilog/

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