URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_24/] [rtl/] [verilog/] - Rev 73

Rev	Log message	Author	Age	Path
50	checks destination address for Unicast, Multicast and Broadcast ops	billditt	8180d 10h	/ethmac/tags/rel_24/rtl/verilog/
48	RxOverRun added to statuses.	mohor	8182d 12h	/ethmac/tags/rel_24/rtl/verilog/
47	HASH0 and HASH1 registers added. Registers address width was changed to 8 bits.	mohor	8182d 12h	/ethmac/tags/rel_24/rtl/verilog/
46	HASH0 and HASH1 registers added.	mohor	8182d 12h	/ethmac/tags/rel_24/rtl/verilog/
43	Tx status is written back to the BD.	mohor	8183d 20h	/ethmac/tags/rel_24/rtl/verilog/
42	Rx status is written back to the BD.	mohor	8186d 13h	/ethmac/tags/rel_24/rtl/verilog/
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8188d 15h	/ethmac/tags/rel_24/rtl/verilog/
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8189d 12h	/ethmac/tags/rel_24/rtl/verilog/
39	Tx part finished. TxStatus needs to be fixed. Pause request needs to be added.	mohor	8193d 16h	/ethmac/tags/rel_24/rtl/verilog/
38	Initial version. Equals to eth_wishbonedma.v at this moment.	mohor	8202d 18h	/ethmac/tags/rel_24/rtl/verilog/