URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_26/] [rtl/] [verilog/] - Rev 244

Rev	Log message	Author	Age	Path
203	Virtual Silicon RAM might be used in the ASIC implementation of the ethernet core.	mohor	7944d 23h	/ethmac/tags/rel_26/rtl/verilog/
202	CsMiss added. When address between 0x800 and 0xfff is accessed within Ethernet Core, error acknowledge is generated.	mohor	7948d 00h	/ethmac/tags/rel_26/rtl/verilog/
168	CarrierSenseLost bug fixed when operating in full duplex mode.	mohor	7956d 03h	/ethmac/tags/rel_26/rtl/verilog/
167	Sometimes both RxB_IRQ and RxE_IRQ were activated. Bug fixed.	mohor	7957d 03h	/ethmac/tags/rel_26/rtl/verilog/
166	Reception is possible after RxPointer is read and not after BD is read. For that reason RxBDReady is changed to RxReady. Busy_IRQ interrupt connected. When there is no RxBD ready and frame comes, interrupt is generated.	mohor	7958d 04h	/ethmac/tags/rel_26/rtl/verilog/
165	HASH improvement needed.	mohor	7958d 07h	/ethmac/tags/rel_26/rtl/verilog/
164	Ethernet debug registers removed.	mohor	7958d 07h	/ethmac/tags/rel_26/rtl/verilog/
161	Error acknowledge is generated when accessing BDs and RST bit in the MODER register (r_Rst) is set.	mohor	7959d 04h	/ethmac/tags/rel_26/rtl/verilog/
160	error acknowledge cycle termination added to display.	mohor	7959d 05h	/ethmac/tags/rel_26/rtl/verilog/
159	Async reset for WB_ACK_O removed (when core was in reset, it was impossible to access BDs). RxPointers and TxPointers names changed to be more descriptive. TxUnderRun synchronized.	mohor	7960d 01h	/ethmac/tags/rel_26/rtl/verilog/