URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_5/] [rtl/] [verilog/] - Rev 143

Rev	Log message	Author	Age	Path
114	EXTERNAL_DMA removed. External DMA not supported.	mohor	7986d 17h	/ethmac/tags/rel_5/rtl/verilog/
113	RxPointer bug fixed.	mohor	7993d 09h	/ethmac/tags/rel_5/rtl/verilog/
112	Previous bug wasn't succesfully removed. Now fixed.	mohor	7993d 22h	/ethmac/tags/rel_5/rtl/verilog/
111	Master state machine had a bug when switching from master write to master read.	mohor	7994d 12h	/ethmac/tags/rel_5/rtl/verilog/
110	m_wb_cyc_o signal released after every single transfer.	mohor	7994d 15h	/ethmac/tags/rel_5/rtl/verilog/
109	Comment removed.	mohor	7994d 15h	/ethmac/tags/rel_5/rtl/verilog/
106	Outputs registered. Reset changed for eth_wishbone module.	mohor	8062d 01h	/ethmac/tags/rel_5/rtl/verilog/
105	Compiler directives added. Tx and Rx fifo size incremented. A "late collision" bug fixed.	mohor	8071d 03h	/ethmac/tags/rel_5/rtl/verilog/
104	FCS should not be included in NibbleMinFl.	mohor	8072d 21h	/ethmac/tags/rel_5/rtl/verilog/
103	Wishbone signals are registered when ETH_REGISTERED_OUTPUTS is selected in eth_defines.v	mohor	8072d 21h	/ethmac/tags/rel_5/rtl/verilog/