URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [rel_6/] [rtl/] [verilog/] - Rev 127

Rev	Log message	Author	Age	Path
100	Generic ram or Xilinx ram can be used in fifo (selectable by setting ETH_FIFO_XILINX in eth_defines.v).	mohor	8077d 15h	/ethmac/tags/rel_6/rtl/verilog/
97	Small typo fixed.	lampret	8101d 13h	/ethmac/tags/rel_6/rtl/verilog/
96	Any address can be used for Tx and Rx BD pointers. Address does not need to be aligned.	mohor	8105d 13h	/ethmac/tags/rel_6/rtl/verilog/
95	md_padoen_o changed to md_padoe_o. Signal was always active high, just name was incorrect.	mohor	8105d 15h	/ethmac/tags/rel_6/rtl/verilog/
94	When clear and read/write are active at the same time, cnt and pointers are set to 1.	mohor	8105d 15h	/ethmac/tags/rel_6/rtl/verilog/
93	When in promiscous mode some frames were not received correctly. Fixed.	mohor	8110d 14h	/ethmac/tags/rel_6/rtl/verilog/
92	Some defines that are used in testbench only were moved to tb_eth_defines.v file.	mohor	8111d 16h	/ethmac/tags/rel_6/rtl/verilog/
91	Comments in Slovene language removed.	mohor	8111d 16h	/ethmac/tags/rel_6/rtl/verilog/
90	casex changed with case, fifo reset changed.	mohor	8111d 16h	/ethmac/tags/rel_6/rtl/verilog/
88	rx_fifo was not always cleared ok. Fixed.	mohor	8121d 13h	/ethmac/tags/rel_6/rtl/verilog/