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[/] [ethmac/] [tags/] [runing_under_uclinux/] [rtl/] [verilog/] - Rev 106

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Rev Log message Author Age Path
83 MAC address recognition was not correct (bytes swaped). mohor 8128d 12h /ethmac/tags/runing_under_uclinux/rtl/verilog/
82 Byte ordering changed (Big Endian used). casex changed with case because
Xilinx Foundation had problems. Tested in HW. It WORKS.
mohor 8128d 14h /ethmac/tags/runing_under_uclinux/rtl/verilog/
80 Small fixes for external/internal DMA missmatches. mohor 8132d 16h /ethmac/tags/runing_under_uclinux/rtl/verilog/
79 RetryCntLatched was unused and removed from design mohor 8132d 17h /ethmac/tags/runing_under_uclinux/rtl/verilog/
78 WB_SEL_I was unused and removed from design mohor 8132d 17h /ethmac/tags/runing_under_uclinux/rtl/verilog/
77 Interrupts changed mohor 8132d 17h /ethmac/tags/runing_under_uclinux/rtl/verilog/
76 Interrupts changed in the top file mohor 8132d 17h /ethmac/tags/runing_under_uclinux/rtl/verilog/
75 r_Bro is used for accepting/denying frames mohor 8132d 17h /ethmac/tags/runing_under_uclinux/rtl/verilog/
74 Reset values are passed to registers through parameters mohor 8132d 17h /ethmac/tags/runing_under_uclinux/rtl/verilog/
73 Number of interrupts changed mohor 8132d 17h /ethmac/tags/runing_under_uclinux/rtl/verilog/

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