OpenCores
URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [tags/] [runing_under_uclinux/] [rtl/] [verilog/] - Rev 96

Rev

Go to most recent revision

Filtering Options

Clear current filter

Rev Log message Author Age Path
74 Reset values are passed to registers through parameters mohor 8147d 08h /ethmac/tags/runing_under_uclinux/rtl/verilog/
73 Number of interrupts changed mohor 8147d 08h /ethmac/tags/runing_under_uclinux/rtl/verilog/
72 Retry is not activated when a Tx Underrun occured mohor 8151d 11h /ethmac/tags/runing_under_uclinux/rtl/verilog/
70 Small fixes. mohor 8155d 13h /ethmac/tags/runing_under_uclinux/rtl/verilog/
69 Define missmatch fixed. mohor 8156d 11h /ethmac/tags/runing_under_uclinux/rtl/verilog/
68 Registered trimmed. Unused registers removed. mohor 8157d 10h /ethmac/tags/runing_under_uclinux/rtl/verilog/
67 EXTERNAL_DMA used instead of WISHBONE_DMA. mohor 8157d 11h /ethmac/tags/runing_under_uclinux/rtl/verilog/
65 Testbench fixed, code simplified, unused signals removed. mohor 8157d 17h /ethmac/tags/runing_under_uclinux/rtl/verilog/
64 Status was not written correctly when frames were discarted because of
address mismatch.
mohor 8158d 07h /ethmac/tags/runing_under_uclinux/rtl/verilog/
63 RxAbort is connected differently. mohor 8158d 10h /ethmac/tags/runing_under_uclinux/rtl/verilog/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.