URL https://opencores.org/ocsvn/ethmac/ethmac/trunk

Subversion Repositories ethmac

[/] [ethmac/] [trunk/] [rtl/] [verilog/] - Rev 70

Rev	Log message	Author	Age	Path
47	HASH0 and HASH1 registers added. Registers address width was changed to 8 bits.	mohor	8146d 01h	/ethmac/trunk/rtl/verilog/
46	HASH0 and HASH1 registers added.	mohor	8146d 01h	/ethmac/trunk/rtl/verilog/
43	Tx status is written back to the BD.	mohor	8147d 08h	/ethmac/trunk/rtl/verilog/
42	Rx status is written back to the BD.	mohor	8150d 01h	/ethmac/trunk/rtl/verilog/
41	non-DMA host interface added. Select the right configutation in eth_defines.	mohor	8152d 03h	/ethmac/trunk/rtl/verilog/
40	Both rx and tx part are finished. Tested with wb_clk_i between 10 and 200 MHz. Statuses, overrun, control frame transmission and reception still need to be fixed.	mohor	8153d 01h	/ethmac/trunk/rtl/verilog/
39	Tx part finished. TxStatus needs to be fixed. Pause request needs to be added.	mohor	8157d 05h	/ethmac/trunk/rtl/verilog/
38	Initial version. Equals to eth_wishbonedma.v at this moment.	mohor	8166d 07h	/ethmac/trunk/rtl/verilog/
37	Link in the header changed.	mohor	8166d 07h	/ethmac/trunk/rtl/verilog/
34	RX_BD_NUM changed to TX_BD_NUM (holds number of TX descriptors instead of the number of RX descriptors).	mohor	8215d 03h	/ethmac/trunk/rtl/verilog/