URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

Subversion Repositories ha1588

[/] [ha1588/] [tags/] [v1p2/] [sim/] - Rev 77

Rev	Log message	Author	Age	Path
31	Added hand-shaking for the TSU data reading.	edn_walter	4476d 04h	/ha1588/tags/v1p2/sim/
30	Timestamp format in the queue = msgId_4bit + seqId_16bit + null_8bit + timeStamp1s_4bit + null_2bit + timeStamp1ns_30bit	edn_walter	4476d 04h	/ha1588/tags/v1p2/sim/
29	Added multicycle timing constraint to ptp_parser.v, which works at data rate of (32bit * 4 gmii_clk cycle). Fmax can exceed 250MHz.	edn_walter	4476d 04h	/ha1588/tags/v1p2/sim/
26	Updated test case.	edn_walter	4478d 05h	/ha1588/tags/v1p2/sim/
24	Added test cases for top-level testbench to cover both RTC and TSU.	edn_walter	4479d 06h	/ha1588/tags/v1p2/sim/
23	Added CDC hand-shaking for RTC time reading operation.	edn_walter	4480d 00h	/ha1588/tags/v1p2/sim/
22	RTC reset will clear ACC counter, but not clear ACC counter incremental.	edn_walter	4480d 04h	/ha1588/tags/v1p2/sim/
21	Added structure for top-level simulation. Systemverilog DPI will be used to emulate the SW operation of PTP application.	edn_walter	4481d 00h	/ha1588/tags/v1p2/sim/
19	Added pipeline registers to Real Time Clock module to improve timing.	edn_walter	4485d 05h	/ha1588/tags/v1p2/sim/
15	Renamed module name for tsu and rtc. Added folder for reg and top. Added folder for sopc, preparing for Altera SOPC Builder customized component.	edn_walter	4492d 00h	/ha1588/tags/v1p2/sim/