URL https://opencores.org/ocsvn/ha1588/ha1588/trunk

Subversion Repositories ha1588

[/] [ha1588/] [trunk/] [sim/] - Rev 69

Rev	Log message	Author	Age	Path
41	Added pre-adder to the accumulator to cut down critical timing path.	edn_walter	4440d 21h	/ha1588/trunk/sim/
39	1. Added memory map and feature description. 2. Separated TX RX TSU register addresses.	edn_walter	4441d 00h	/ha1588/trunk/sim/
38	1. Redefined the memory map. See changes in reg.v and ptp_drv_bfm.c. 2. Added adj_done signal for CPU polling. 3. Making time_acc_modulo a constant = 256,000,000,000. No need to change it from software side.	edn_walter	4441d 22h	/ha1588/trunk/sim/
37	Timestamp format in the queue = null_16bit + timeStamp1s_48bit + timeStamp1ns_32bit + msgId_4bit + ckSum_12bit + seqId_16bit	edn_walter	4442d 01h	/ha1588/trunk/sim/
36	TSU testbench is now self-checking. Test result is reported at end of simulation.	edn_walter	4442d 20h	/ha1588/trunk/sim/
35	Added support for stacked MPLS UDP/IPv4/IPv6 PTP packets.	edn_walter	4443d 19h	/ha1588/trunk/sim/
34	Added LGPL file header to all copyrighted files.	edn_walter	4443d 22h	/ha1588/trunk/sim/
33	Redefined memory map. RTC and TSU now have separate address spans, can be easily divided into to independent modules.	edn_walter	4443d 23h	/ha1588/trunk/sim/
32	Added PTP standard time format output to the top module. Can be connected to external modules.	edn_walter	4444d 02h	/ha1588/trunk/sim/
31	Added hand-shaking for the TSU data reading.	edn_walter	4444d 19h	/ha1588/trunk/sim/