URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] - Rev 163

Rev	Log message	Author	Age	Path
143	'adventure' sample by default will log from 0xb0000000 and simulation length is now longer	ja_rd	4816d 07h	/ion/
142	'Adventure' bootstrap code now enables the cache (and runs noticeably faster on DE-1 board)	ja_rd	4816d 07h	/ion/
141	BUG FIX in cache: cpu stall logic was missing key case 2nd SW in a (cached) row was not being stalled	ja_rd	4816d 07h	/ion/
140	BUG FIX in cpu: MTCx was using Rs as source instead of Rt BUG FIX in cpu: cached sequences of S* were failing, byte_we logic was wrong	ja_rd	4816d 07h	/ion/
139	updated simulation & synthesis pre-generated entities ('hello' code sample)	ja_rd	4817d 00h	/ion/
138	updated simulation & synthesis pre-generated entities ('hello' code sample)	ja_rd	4817d 00h	/ion/
137	Updated TB2 for new cache interface ('unmapped' signal)	ja_rd	4817d 01h	/ion/
136	Added debug output to synthesizable MPU template, and connected debug signals to LEDs	ja_rd	4817d 01h	/ion/
135	Added debug output to synthesizable MPU template.	ja_rd	4817d 01h	/ion/
134	Added 'unmapped access' flag to CPU core, meant for debug mostly. Eventually this flag will trigger an interrupt.	ja_rd	4817d 01h	/ion/