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Rev Log message Author Age Path
154 fixed log trigger address in hello makefile ja_rd 4780d 15h /ion/
153 Added R3000 compatible support for kernel/user state:
- Implemented KU/IE plus KUp/IEp and KUo/IEo status bits
- Updated startup and test code to account for changes
- Implemented bit DID NOT TEST rfe instruction (not used in code)
- Access to CP0 in user mode triggers 'CpU' trap
- Updated software simulator

Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.		 ja_rd 4780d 15h /ion/
152 Added R3000 compatible support for kernel/user state:
- Implemented KU/IE plus KUp/IEp and KUo/IEo status bits
- Updated startup and test code to account for changes
- Implemented bit DID NOT TEST rfe instruction (not used in code)
- Access to CP0 in user mode triggers 'CpU' trap
- Updated software simulator

Besides, the logging of HI/LO register changes has been temporarily disabled, there's an unfixed bug in it.		 ja_rd 4780d 15h /ion/
151 BUG FIX: major bugs fixed in cache module
1.- sram address was wrong (leftover from previous version)
2.- writes to unmapped areas were blocking the cache
3.- Sequence SW,LW produced a RAW data hazard in some cases		 ja_rd 4780d 15h /ion/
150 Bug fix: added missing nop in vacant branch delay slot ja_rd 4781d 13h /ion/
149 changed size of simulated flash in opcodes sample code ja_rd 4781d 13h /ion/
148 Added optional cache support to 'opcodes' test.
Updated simulation length accordingly.		 ja_rd 4783d 04h /ion/
147 SW simulator updated to latest HW revision
(plus a few mistakes corrected: wrongly commented out lines, mostly)		 ja_rd 4783d 04h /ion/
146 Added D-Cache setup code to 'adventure' bootstrap code
(redundant since common C startup code already does it but...)		 ja_rd 4783d 05h /ion/
145 MAJOR UPDATE: first version of D-Cache ja_rd 4783d 05h /ion/

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