URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] - Rev 56

Rev	Log message	Author	Age	Path
36	pre-generated simulation test bench TB1 updated for compatibility to other changes	ja_rd	4946d 21h	/ion/
35	CPU mem_wait logic updated to work with cache	ja_rd	4946d 21h	/ion/
34	default data address moved to 0x80000000 makefiles and readme files updated accordingly	ja_rd	4946d 21h	/ion/
33	bin2hdl now can initialize 16-bit wide memories	ja_rd	4946d 21h	/ion/
32	slite: catch 1-instruction endless loops now can run unattended; will stop at the end of main()	ja_rd	4946d 22h	/ion/
31	Major refactor in slite: supports memory map with more than 1 block indentation made homogeneous unused code removed	ja_rd	4946d 22h	/ion/
30	Completed decoding of instructions (to prevent side effects of invalid opcodes)	ja_rd	4948d 18h	/ion/
29	opcode test updated: supports CP0 cause register and traps in delay slots tests that traps abort next instruction in all cases	ja_rd	4948d 19h	/ion/
28	Core updated: supports CP0 cause register and traps in delay slots traps abort next instruction in all cases (incl. jumps/L/S)	ja_rd	4948d 19h	/ion/
27	SW simulator updated: now supports CP0 cause register and traps in delay slots	ja_rd	4948d 21h	/ion/