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Rev Log message Author Age Path
66 Code samples:
Updated all code samples to use TB2 template and new memory map
ja_rd 4909d 06h /ion/
65 Fixed io input mux in MPU template 1 ja_rd 4909d 06h /ion/
64 Refactored memory decoding logic
(wait states and read-only attributes unimplemented yet)
ja_rd 4909d 06h /ion/
63 DE-1 demo top module:
added registers for SD interface, switches and 7-seg display
ja_rd 4909d 06h /ion/
62 CPU fixed:
fixed bug in EPC load logic relative to mem_wait stalls
parametrized reset and trap vector addresses
ja_rd 4909d 07h /ion/
61 SW simulator updated:
new mips-1 memory map and trap addresses
slightly better command line argument parsing
ja_rd 4909d 07h /ion/
60 Forgot to upload new TB package!!
Without this, simulations don't work...
ja_rd 4909d 07h /ion/
59 cleaned up top vhdl module of demo
moved reset sync ff chain to top module
updated pre-generated demo file
ja_rd 4910d 20h /ion/
58 Cleaned up cache stub code ja_rd 4911d 07h /ion/
57 updated precompiled demo:
single 32-bit BROM instead of 4x8-bit
ja_rd 4911d 08h /ion/

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