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Rev Log message Author Age Path
72 Fixed stupid bug in SRAM write cycles (setup time violated)
Wait states implemented for SRAM wait and read cycles
ja_rd 4906d 01h /ion/
71 Doc updated to reflect last changes ja_rd 4906d 12h /ion/
70 updated CodeBlocks project file ja_rd 4906d 13h /ion/
69 Updated simulation scripts
Obsolete sim script removed
ja_rd 4906d 13h /ion/
68 Updated pre-generated vhdl files ja_rd 4906d 13h /ion/
67 Deprecated files:
Marked three files as unused, to be removed
ja_rd 4906d 13h /ion/
66 Code samples:
Updated all code samples to use TB2 template and new memory map
ja_rd 4906d 13h /ion/
65 Fixed io input mux in MPU template 1 ja_rd 4906d 13h /ion/
64 Refactored memory decoding logic
(wait states and read-only attributes unimplemented yet)
ja_rd 4906d 13h /ion/
63 DE-1 demo top module:
added registers for SD interface, switches and 7-seg display
ja_rd 4906d 13h /ion/

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