URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] - Rev 54

Rev	Log message	Author	Age	Path
34	default data address moved to 0x80000000 makefiles and readme files updated accordingly	ja_rd	4916d 03h	/ion/trunk/
33	bin2hdl now can initialize 16-bit wide memories	ja_rd	4916d 03h	/ion/trunk/
32	slite: catch 1-instruction endless loops now can run unattended; will stop at the end of main()	ja_rd	4916d 04h	/ion/trunk/
31	Major refactor in slite: supports memory map with more than 1 block indentation made homogeneous unused code removed	ja_rd	4916d 04h	/ion/trunk/
30	Completed decoding of instructions (to prevent side effects of invalid opcodes)	ja_rd	4918d 00h	/ion/trunk/
29	opcode test updated: supports CP0 cause register and traps in delay slots tests that traps abort next instruction in all cases	ja_rd	4918d 01h	/ion/trunk/
28	Core updated: supports CP0 cause register and traps in delay slots traps abort next instruction in all cases (incl. jumps/L/S)	ja_rd	4918d 01h	/ion/trunk/
27	SW simulator updated: now supports CP0 cause register and traps in delay slots	ja_rd	4918d 03h	/ion/trunk/
26	changes in simulation test benches: Simulation length now configurable from the python script Console output logged to file, not to modelsim's window	ja_rd	4918d 06h	/ion/trunk/
25	opcode test: HO and LO registers tested along with mul/div and not separately	ja_rd	4918d 06h	/ion/trunk/