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[/] [ion/] [trunk/] [vhdl/] - Rev 144

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Rev Log message Author Age Path
98 CPU rd and wr data address buses unified ja_rd 4885d 02h /ion/trunk/vhdl/
96 CPU rd and wr data address buses unified ja_rd 4885d 02h /ion/trunk/vhdl/
95 BUG FIX: cache stub properly handles all kind of cycles now ja_rd 4895d 23h /ion/trunk/vhdl/
94 Pregenerated demo 'hello' files updated ja_rd 4895d 23h /ion/trunk/vhdl/
85 BUG FIX: log2 function was wrong ja_rd 4895d 23h /ion/trunk/vhdl/
84 Added 'trigger address' for file logging to both the
vhdl TB and the python script
ja_rd 4895d 23h /ion/trunk/vhdl/
83 BUG FIX: LHU was not doing sign extension properly
BUG FIX: SLTIU decoding was wrong
ja_rd 4895d 23h /ion/trunk/vhdl/
82 bug fix: SLTI wasn't working properly in some cases ja_rd 4897d 23h /ion/trunk/vhdl/
81 Added a wait state to the SRAM area for the DE-1 demo code ja_rd 4904d 18h /ion/trunk/vhdl/
80 Stub cache fixed
Now supports code refills from static 16- and 8- bit memory
Plus many mirror corrections
ja_rd 4904d 18h /ion/trunk/vhdl/

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