URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [vhdl/] - Rev 200

Rev	Log message	Author	Age	Path
134	Added 'unmapped access' flag to CPU core, meant for debug mostly. Eventually this flag will trigger an interrupt.	ja_rd	4825d 12h	/ion/trunk/vhdl/
133	First draft of the SDRAM controller (Still unused in the code working base)	ja_rd	4828d 09h	/ion/trunk/vhdl/
132	Fixed bug in stall logic (stall for back-to-back SW instructions was wrong)	ja_rd	4828d 09h	/ion/trunk/vhdl/
129	updated pregenerated demo ('hello')	ja_rd	4828d 09h	/ion/trunk/vhdl/
128	updated precompiled simulation testbench	ja_rd	4828d 10h	/ion/trunk/vhdl/
126	added SDRAM verilog simulation model	ja_rd	4828d 10h	/ion/trunk/vhdl/
121	CPU code reorganized a bit No new logic, just a few swapped lines and new comments	ja_rd	4874d 09h	/ion/trunk/vhdl/
120	Updated main package with lots of wait states for all areas	ja_rd	4883d 12h	/ion/trunk/vhdl/
119	Updated pre-generated simulation and synthesis demos	ja_rd	4883d 12h	/ion/trunk/vhdl/
116	Updated demo 'top' file for DE-1 board - Added reset button debouncing - Added template for using different clock input - Uses clock rate generic	ja_rd	4883d 13h	/ion/trunk/vhdl/