URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [vhdl/] - Rev 212

Rev	Log message	Author	Age	Path
145	MAJOR UPDATE: first version of D-Cache	ja_rd	4804d 06h	/ion/trunk/vhdl/
141	BUG FIX in cache: cpu stall logic was missing key case 2nd SW in a (cached) row was not being stalled	ja_rd	4805d 20h	/ion/trunk/vhdl/
140	BUG FIX in cpu: MTCx was using Rs as source instead of Rt BUG FIX in cpu: cached sequences of S* were failing, byte_we logic was wrong	ja_rd	4805d 20h	/ion/trunk/vhdl/
139	updated simulation & synthesis pre-generated entities ('hello' code sample)	ja_rd	4806d 13h	/ion/trunk/vhdl/
138	updated simulation & synthesis pre-generated entities ('hello' code sample)	ja_rd	4806d 13h	/ion/trunk/vhdl/
136	Added debug output to synthesizable MPU template, and connected debug signals to LEDs	ja_rd	4806d 13h	/ion/trunk/vhdl/
134	Added 'unmapped access' flag to CPU core, meant for debug mostly. Eventually this flag will trigger an interrupt.	ja_rd	4806d 13h	/ion/trunk/vhdl/
133	First draft of the SDRAM controller (Still unused in the code working base)	ja_rd	4809d 11h	/ion/trunk/vhdl/
132	Fixed bug in stall logic (stall for back-to-back SW instructions was wrong)	ja_rd	4809d 11h	/ion/trunk/vhdl/
129	updated pregenerated demo ('hello')	ja_rd	4809d 11h	/ion/trunk/vhdl/