OpenCores
URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [vhdl/] - Rev 252

Rev

Filtering Options

Clear current filter

Rev Log message Author Age Path
212 BUG FIX: sequences of back-to-back I/O reads or writes didn't work.
The stall conditions were wrong for those cases.
Minor cleanup of the comments		 ja_rd 4374d 22h /ion/trunk/vhdl/
211 Included a simulated block of I/O regs in the test bench for easing some cache tests. ja_rd 4374d 23h /ion/trunk/vhdl/
207 Simulation memories now modelled with shared variables and not signals.
This improves simulation speed of large programs (e.g. Adventure) by orders of magnitude		 ja_rd 4653d 18h /ion/trunk/vhdl/
206 Fixed SygnalSpy function calls for compatibility with older versions of Modelsim ja_rd 4653d 18h /ion/trunk/vhdl/
205 Fixed bug in test bench interface to CPU ja_rd 4674d 17h /ion/trunk/vhdl/
201 Minor fixes to code comments ja_rd 4688d 17h /ion/trunk/vhdl/
200 CPU interrupt input changed to 8-bit vector
Other modules changed accordingly
Interrupts still missing; this is just preparing the interface		 ja_rd 4688d 17h /ion/trunk/vhdl/
194 Removed deprecated files from old TB version ja_rd 4690d 09h /ion/trunk/vhdl/
193 Major test bench reorganization:
1.- TB now uses same object code as synthesizable demo.
2.- TB now simulates full MPU system.
3.- Console logging moved to TB package.
4.- Code sample makefiles and modelsim script updated accordingly.		 ja_rd 4690d 09h /ion/trunk/vhdl/
191 Separated object code stuff from mcu entity
Object code related stuff now lives in separate file
Makefiles for code samples updated accordingly
Old mcu template deprecated but still in place		 ja_rd 4694d 18h /ion/trunk/vhdl/

< Prev 1 2

Show All

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.