URL https://opencores.org/ocsvn/ion/ion/trunk

Subversion Repositories ion

[/] [ion/] [trunk/] [vhdl/] - Rev 86

Rev	Log message	Author	Age	Path
47	Pre-generated simulation test benches updated	ja_rd	4911d 20h	/ion/trunk/vhdl/
46	First version of cache: stub, 1-word cache Stub cache tested on simulation and HW, just a stub Adapted CPU stall logic to 1st version of cache Adapted all other modules for compatibility with cache	ja_rd	4911d 20h	/ion/trunk/vhdl/
43	added comments to dummy 'cache' stub	ja_rd	4914d 04h	/ion/trunk/vhdl/
42	Added cache stub module, plus related test bench	ja_rd	4915d 23h	/ion/trunk/vhdl/
40	pre-generated 'hello' demo updated	ja_rd	4915d 23h	/ion/trunk/vhdl/
37	functions added to package for standard address decoding	ja_rd	4915d 23h	/ion/trunk/vhdl/
36	pre-generated simulation test bench TB1 updated for compatibility to other changes	ja_rd	4915d 23h	/ion/trunk/vhdl/
35	CPU mem_wait logic updated to work with cache	ja_rd	4915d 23h	/ion/trunk/vhdl/
30	Completed decoding of instructions (to prevent side effects of invalid opcodes)	ja_rd	4917d 20h	/ion/trunk/vhdl/
28	Core updated: supports CP0 cause register and traps in delay slots traps abort next instruction in all cases (incl. jumps/L/S)	ja_rd	4917d 22h	/ion/trunk/vhdl/