URL https://opencores.org/ocsvn/m1_core/m1_core/trunk

Subversion Repositories m1_core

[/] [m1_core/] [trunk/] [hdl/] - Rev 61

Rev	Log message	Author	Age	Path
20	Used only lower bits also for SRAV instruction.	fafa1971	5820d 06h	/m1_core/trunk/hdl/
19	Added changes suggested by Paolo Piscopo & Simone Lunardo to fix the bugs they found.	fafa1971	5830d 02h	/m1_core/trunk/hdl/
18	Limited range of SHAMT (shift amount) to be only 5 bits ([4:0])	fafa1971	5830d 02h	/m1_core/trunk/hdl/
16	Corrected some bugs found by Simone Lunardo and Paolo Piscopo.	fafa1971	5874d 01h	/m1_core/trunk/hdl/
15	Added default case for ALU.	fafa1971	5874d 01h	/m1_core/trunk/hdl/
13	Final version of synthesis script at 250 MHz.	fafa1971	5951d 00h	/m1_core/trunk/hdl/
12	New synthesis script.	fafa1971	5951d 01h	/m1_core/trunk/hdl/
7	It should not stay here!	fafa1971	5967d 03h	/m1_core/trunk/hdl/
6	Removed old CVS branches from CPU code.	fafa1971	5967d 03h	/m1_core/trunk/hdl/
2	First public release	fafa1971	5967d 03h	/m1_core/trunk/hdl/