Rev |
Log message |
Author |
Age |
Path |
60 |
Selection of memory model or implementation memory is now made on minsoc_bench_defines.v. It is done by a definition instead of including different files for simulation.
minsoc_bench_defines.v definition of reset level was not correct. It based the level decision on defineds POSITIVE_RESET or NEGATIVE_RESET, which couldn't be defined by then, since minsoc_defines.v is not included in minsoc_bench_defines.v. The decision has been moved to minsoc_bench.v and made a localparam instead of a definition. |
rfajardo |
4786d 07h |
/minsoc/tags/release-1.0/ |
59 |
undefinition of NEGATIVE_RESET on minsoc_bench_defines.v cannot affect other inclusions of minsoc_defines.v. Instead, the testbench now works with the right reset level to avoid the implementation ordering problem. |
rfajardo |
4786d 07h |
/minsoc/tags/release-1.0/ |
58 |
Standard definitions depended on implementation order. Now, this should be solved.
minsoc_bench_defines.v: when setting reset to be positive (`define POSITIVE_RESET), NEGATIVE_RESET is undefined. This override the implementation order, so that independent of it, POSITIVE_RESET will be used.
minsoc_defines.v: when setting GENERIC_FPGA, FPGA_TAP and FPGA_CLOCK_DIVISION are undefined. This way, even if FPGA_TAP would come prior to GENERIC_TAP on the correspondent implementation, GENERIC_TAP would still be selected.
IMPORTANT: GENERIC_MEMORY must still be implemented first on minsoc_onchip_ram.v, because FPGA's memory is automatically selected from other definitions and cannot be undefined a priori. Since some other memory types can be selected, there is no trivial solution. However, this shouldn't be a big problem, since the beginning of this file will probably not be modified. |
rfajardo |
4786d 07h |
/minsoc/tags/release-1.0/ |
57 |
If a FPGA manufacturer is selected, the FPGA families of other manufacturers are automatically ignored.
Some updated to comments.
CLOCK_DIVISOR back to 5. The number does not matter much, but 1 is a bad standard number, since it should never be selected. Comment says, use NO_CLOCK_DIVISION instead.
Changing standard FPGA back to Xilinx and Spartan3A. I'm only doing this because the synthesis examples page of wiki still assume this FPGA to be standardly selected. |
rfajardo |
4786d 08h |
/minsoc/tags/release-1.0/ |
56 |
Macros for all Altera family devices and pll instantiation |
javieralso |
4793d 07h |
/minsoc/tags/release-1.0/ |
55 |
Adjusting Makefiles to compile correctly with new firmware updates.
1) except.o not included into libsupport.a.
2) libsupport.a linked to except.o, now in correct order: ld libsupport.a except.o -o executable (not the other way around)
3) int.c was not being compiled because of a #ifdef which is not set anywhere |
rfajardo |
4794d 15h |
/minsoc/tags/release-1.0/ |
54 |
Moving spr_defs.h to or1200.h |
ConX. |
4794d 17h |
/minsoc/tags/release-1.0/ |
53 |
Indentation, deleting redundant files and adding externals |
ConX. |
4794d 18h |
/minsoc/tags/release-1.0/ |
52 |
Altera ALTPLL Megafunction Instantiation |
javieralso |
4803d 08h |
/minsoc/tags/release-1.0/ |
51 |
sw/support/uart.c: Changing the order of writes to the Divisor Latch of UART. (Thanks Ramkumar) |
rfajardo |
4809d 21h |
/minsoc/tags/release-1.0/ |