Rev |
Log message |
Author |
Age |
Path |
39 |
FAQ:
-Adv_jtag_bridge self test fails?
-included now SoC flow mistakes
-forgetting to upload the bitfile
-leaving clock unconnected
-older information is now under "Known Issues" right below of SoC flow mistakes
Software:
-eth: included eth.h is from drivers and not from this directory. eth.h from this directory is old and has been removed.
-uart: included uart.h is from drivers and not from this directory. uart.h from this directory is old and has been removed. |
rfajardo |
4983d 20h |
/minsoc/trunk/ |
38 |
Small update to HOWTO: advices now to also include the ucf (pinout) file, for forgetful people :-).
FAQ: Added another option (hint) as a solution for people with on-board Xilinx USB cables, which do not reset.
uart.c: now uses the IRQ line definition instead of the line number directly. |
rfajardo |
5018d 19h |
/minsoc/trunk/ |
37 |
README.txt added, describing the installation and set-up processes. Also describing to use the FAQ or forum when you have problems and finally to read minsoc.pdf (the documentation) to understand the system after everything works, to know what to do next.
Clean-up of sw/utils, removing unused sources and files.
Update of sw/drivers/eth.c, direct casting to avoid compile warnings.
FAQ extended and with more links to the threads giving the solutions.
Synthesis examples inform that the firmware tweak for Spartan3E Starter Kit using Ethernet only works for system version up to 35.
minsoc.pdf and webpage now uses FPGA generic and specific codes instead of FPGA independent and dependent codes, because it suits it better. |
rfajardo |
5049d 06h |
/minsoc/trunk/ |
36 |
utils: -adding a 32 to 8 bit Wishbone bridge to connect 8 bit modules to the MinSoC interconnect.
-adding a Linux driver for parallel cables for the adv_jtag_bridge. It circumvents the necessity of privilege to run adv_jtag_bridge with cables xpc3 and xess.
sw/support: support library has been made completely standalone. That means, it is now independent from uClib and/or newlib. Thanks to Wojciech A. Koszek for his contribution on this.
sw/drivers: a driver library has been included, which supply drivers for the OpenRISC timer; and for UART, Ethernet, I2C, and CAN modules from OpenCores.
sw/uart and sw/eth: they don't provide code to control the UART and Ethernet controllers anymore. They use the drivers library instead.
Documentation:
-FAQ extended:
-table of contents
-explanation of how to use the 32 to 8 bit Wishbone bridge
-how to make adv_jtag_bridge work without privilege requirement for xess or xpc3
-explanation of locking problem of xpc_usb cable
-explanation of what to do if the cable is built on-board
-INSTALL:
-patching of gdb only required if version is 6.8, explanation on FAQ now.
-HOWTO:
-instruct to compile drivers library
-remove line numbers information on what to edit, better leave it to be found only by the informed context.
-adv_jtag_bridge execution now without 'sudo'. Note included that 'sudo' is required for Linux and xess or xpc3. Reference to FAQ to avoid this requirement. |
rfajardo |
5050d 02h |
/minsoc/trunk/ |
35 |
minsoc.pdf: -adjusting the date on the page header of MinSoC documentation. It was correct on the front and revision pages, now header adjusted accordingly. |
rfajardo |
5054d 20h |
/minsoc/trunk/ |
34 |
start_server changed: '-t' option of adv_jtag_bridge for vpi connection on simulation removed. or1200_v3 will not pass on CPU self test.
FAQ completed with asked questions since Februrary 2010.
INSTALL informs bsdl files only have to be copied to home directory for Xilinx devices.
synthesis_examples title includes Minimal OpenRISC System on Chip. |
rfajardo |
5064d 05h |
/minsoc/trunk/ |
33 |
Start-up Starter, included in the MinSoC top file, has been updated to three-phase instruction output; instruction assertion, acknowledge assertion, and next instruction with acknowledge deassertion.
Previously it was two-phase with next instruction, instruction assertion and acknowledge assertion together, and acknowledge deassertion.
That is required by the new Wishbone master interface used by OpenRISC release 3. |
rfajardo |
5072d 06h |
/minsoc/trunk/ |
32 |
Documentation revision 1.1, thanks to Wojciech A. Koszek for many comments on it.
Also updating howto, splitint it in INSTALL, HOWTO, FAQ and synthesis_examples, so it should be more clear now what to do when and not to try too much when you don't need. Like everyone was trying to debug the simulation but didn't even test the regular simulation before. Again thanks to Wojciech A. Koszek for his view on this matter. |
rfajardo |
5086d 04h |
/minsoc/trunk/ |
31 |
Adaption to or1200_r3. It is still important to change or1200_defines.v:
-`define OR1200_BOOT_ADR 32'hf0000100 to `define OR1200_BOOT_ADR 32'h00000100 |
rfajardo |
5141d 11h |
/minsoc/trunk/ |
30 |
minsoc SoC documentation had 2 small typo corrections. Performance penalty due to addition of register addresses was a wrong assumption. On project description "is composed by" -> "consists of". Thanks to Wojciech A. Koszek.
howto, at some places the howto did not tell the path from the files being talked about. I tried to always specify the path for every commented file.
Scripts for running the simulation called bash instead of sh. For compatibility reasons sh is now used, this should affect noone. Scripts do not use bash specific commands and generally every UNIX like computer has sh. Thanks again to Wojciech A. Koszek, who adapted that to port it to FreeBSD. |
rfajardo |
5184d 09h |
/minsoc/trunk/ |