URL https://opencores.org/ocsvn/mlite/mlite/trunk

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[/] [mlite/] [trunk/] [vhdl/] - Rev 196

Rev	Log message	Author	Age	Path
117	Part of Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7554d 00h	/mlite/trunk/vhdl/
116	Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7554d 00h	/mlite/trunk/vhdl/
115	Matthias Grunewald's changes for Xilinx FPGA dual-port RAM.	rhoads	7554d 00h	/mlite/trunk/vhdl/
114	Matthias Grunewald's changes to get synthesis to work with Synopsys' FPGA Compiler II.	rhoads	7554d 00h	/mlite/trunk/vhdl/
113	Matthias Grunewald's bug fixes: Branch and compare instructions didn't interpret immediate as signed.	rhoads	7554d 00h	/mlite/trunk/vhdl/
112	Merged Matthias Grunewald's changes to use tri-state for smaller Xilinx FPGA.	rhoads	7554d 00h	/mlite/trunk/vhdl/
108	changed interrupt vector from 0x30 to 0x3c	rhoads	7827d 20h	/mlite/trunk/vhdl/
107	merged rising_edge(clk) statements	rhoads	7827d 20h	/mlite/trunk/vhdl/
106	better test mem_pause	rhoads	7830d 23h	/mlite/trunk/vhdl/
105	better test mem_pause	rhoads	7830d 23h	/mlite/trunk/vhdl/