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Rev Log message Author Age Path
19 Changed simili run to 40us. rhoads 8222d 20h /mlite/trunk/vhdl/
18 Fixed "divu $3,$4". "Div $3,$4" still has bug if $3*$4<0. rhoads 8222d 20h /mlite/trunk/vhdl/
17 Fixed "blez $0,target". Made LWL=LW and SWL=SW. Changed tabs to spaces. rhoads 8222d 20h /mlite/trunk/vhdl/
13 Removed reg_bank configuration control rhoads 8226d 20h /mlite/trunk/vhdl/
12 Better support for dual-port memories, removed old method rhoads 8226d 20h /mlite/trunk/vhdl/
11 Added comment for DEBUG mode rhoads 8226d 20h /mlite/trunk/vhdl/
10 Add pause_in to process dependency, fixes "lw $4,0($4)" rhoads 8226d 20h /mlite/trunk/vhdl/
9 Support for generic_tpram dual-port RAM rhoads 8231d 23h /mlite/trunk/vhdl/
8 Preparing to use dual-port memory for registers. rhoads 8232d 21h /mlite/trunk/vhdl/
7 Made writes 4 cycles, improved mem_ctrl.vhd rhoads 8238d 04h /mlite/trunk/vhdl/

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