URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 45

Rev	Log message	Author	Age	Path
25	first version of new pipeline design. allows for more flexibility in nr of stages. does not support split pipeline support yet. currently only works for single pipeline	JonasDC	4256d 10h	/mod_sim_exp/
24	changed names of top-level module to mod_sim_exp_core	JonasDC	4259d 19h	/mod_sim_exp/
23	added descriptive comments	JonasDC	4259d 20h	/mod_sim_exp/
22	updated the systolic pipeline with descriptive signal names and comments	JonasDC	4262d 14h	/mod_sim_exp/
21	changed x_i signal to xi	JonasDC	4263d 22h	/mod_sim_exp/
20	added comments, changed signal name of x_reg_i to x_reg. File is now according to OC design rules	JonasDC	4263d 22h	/mod_sim_exp/
19	updated files with descriptive comments changed signal names and removed redundant signals in stepping_logic	JonasDC	4268d 17h	/mod_sim_exp/
18	updated stages with comments and renamed some signals for consistency	JonasDC	4269d 16h	/mod_sim_exp/
17	updated files with descriptive comments and removed unnecessary signals in standard stage. Files are now according to OC design rules	JonasDC	4269d 21h	/mod_sim_exp/
16	package with modified generic parameter for register_n	JonasDC	4270d 11h	/mod_sim_exp/