URL https://opencores.org/ocsvn/mod_sim_exp/mod_sim_exp/trunk

Subversion Repositories mod_sim_exp

[/] [mod_sim_exp/] - Rev 84

Rev	Log message	Author	Age	Path
64	added synthesis reports of xilinx and altera	JonasDC	4118d 13h	/mod_sim_exp/
63	now using a generic description of the ram for the memory. the core now should synthesize for al fpga's, no device specific code anymore. tested and synthesizes for altera and xilinx	JonasDC	4118d 13h	/mod_sim_exp/
62	not used anymore	JonasDC	4118d 16h	/mod_sim_exp/
61	updated comments, added optional altera constraint	JonasDC	4118d 16h	/mod_sim_exp/
60	generic version of the fifo, not device specific anymore, uses dpram_generic updated comments of RAM templates.	JonasDC	4121d 06h	/mod_sim_exp/
59	added templates that correctly infer RAM, for dual port en true dual port RAM added general functions file, (used in the two RAM templates)	JonasDC	4121d 06h	/mod_sim_exp/
58	made fifo full a warning	JonasDC	4124d 07h	/mod_sim_exp/
57	new fifo design, is now generic (verified with altera and xilinx) and uses block ram	JonasDC	4124d 07h	/mod_sim_exp/
56	this is a branch to test performance of a new style of ram	JonasDC	4124d 09h	/mod_sim_exp/
55	updated resource usage in comments	JonasDC	4125d 06h	/mod_sim_exp/